1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to nonvolatile memory devices such as flash memory devices.
A claim of priority is made to Korean Patent Application No. 2006-81745 filed on Aug. 28, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Nonvolatile semiconductor memories can be found in a wide variety of consumer and industrial electronic devices such as computer systems, portable devices such as cellular phones and personal digital assistants, cameras, and so on. Nonvolatile semiconductor memories such as flash memory are extremely popular due to benefits such as their large storage capacity, low power consumption, resistance to physical shock, and low cost.
Flash memories are a type of electrically programmable and erasable read only memory (EEPROM), and therefore memory cells in flash memories may be referred to as “flash EEPROM cells”, or simply flash memory cells. In general, a flash memory cell includes a cell transistor comprising a semiconductor substrate (or bulk) of a first conductivity type (e.g., P-type), source and drain regions of a second conductivity type (e.g., N-type), a floating gate formed above a channel region between the source and drain regions and adapted to store electrical charges, and a control gate formed over the floating gate. Because each of the cell transistors includes a floating gate, the cell transistors are commonly referred to as floating gate transistors.
A flash memory cell is typically programmed by applying voltages to the floating gate transistor in the flash memory cell to cause electrons to be trapped in the transistor's floating gate. Conversely, the flash memory cell is typically erased by applying voltages to the floating gate transistor to remove any charges trapped in the floating gate of the floating gate transistor. Without any charges trapped in the floating gate, the floating gate transistor generally has a negative threshold voltage. On the other hand, with charges stored in the floating gate, the threshold voltage of the floating gate transistor increases.
During a program operation, a selected memory cell is designated by a selected word line and a selected bit line. Programming voltages are respectively applied to the selected word line and the selected bit line. In general, the programming voltage for the selected word line is a relatively high voltage and the programming voltage for the selected bit line is a relatively low voltage such as ground. Memory cells that are not selected during the program operation, i.e., non-selected memory cells, are generally designated by non-selected bit lines. However, non-selected memory cells may actually be connected to selected word lines. Program-inhibit voltages are typically applied to the respective non-selected bit lines. For example, the non-selected bit lines may be connected to a power source voltage.
Unfortunately, the respective threshold voltages of non-selected memory cells may be increased when selected memory cells are programmed. One reason for this is that a selected word line connected to any non-selected memory cells may cause charges to be stored in the respective floating gates of the non-selected memory cells. In other words, where a relatively high programming voltage is applied to the selected word line, the high programming voltage is also applied to the control gates of non-selected memory cells connected to the selected word line. As a result, charges may be stored in the control gates of the non-selected memory cells. Such inadvertent programming of non-selected memory cells connected to a selected word line is referred to as “program voltage disturbance”.
Sometimes, non-selected memory cells coupled to non-selected bit lines may even be inadvertently programmed by a pass voltage applied to non-selected word lines. This type of inadvertent programming of non-selected memory cells connected to non-selected word lines and a non-selected bit lines is referred to as “pass voltage disturbance”.
Phenomena such as program voltage disturbance and pass voltage disturbance are described in a variety of references such as, for example, U.S. Pat. Nos. 5,715,194, 6,061,270, 6,661,707, and 7,031,190, the respective disclosures of which are hereby incorporated by reference in their entirety.
The effects of program voltage disturbance and pass voltage disturbance can be roughly illustrated by showing the total number of memory cells storing bad data in a memory device as a function of the level of a pass voltage applied to non-selected memory cells via a non-selected word line. For example, FIG. 1 is a graph illustrating a relationship between a number of inadvertently programmed bits (failed bits) in a flash memory device and a pass voltage Vpass applied to non-selected memory cells. As seen in FIG. 1, where pass voltage Vpass is less than 10V, program voltage disturbance tends to cause a significant number of failed cells, and where pass voltage Vpass is greater than 12V, pass voltage disturbance tends to cause a significant number of failed bits.
A range of pass voltage Vpass between 10V and 12V shows minimal numbers of failed cells in the graph of FIG. 1. This range of pass voltage Vpass where program and pass voltage disturbance are minimal is referred to as a “pass voltage window”.
The above described program voltage and pass voltage disturbances occur during program operations. However, defective bits are generally not detected until a read operation is performed. As a result, where a first program operation is performed and then other program operations are performed on the same memory block as the first program operation without any intervening read operations, defectively programmed memory cells may effectively result in several program operations being wasted.